ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION MEMORY ORGANIZATION Program Memory Internal Data Memory External Data Memory I/O PORT STRUCTURE PULSE WIDTH MODULATED OUTPUTS (PWM) Prescaler frequency control register (PWMP) Pulse Width Register 0 (PWM0) Pulse Width Register 1 (PWM1.
GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION MEMORY ORGANIZATION Program Memory Internal Data Memory External Data Memory I/O PORT STRUCTURE PULSE WIDTH MODULATED OUTPUTS (PWM) Prescaler frequency control register (PWMP) Pulse Width Register 0 (PWM0) Pulse Width Register 1 (PWM1) ANALOG-TO-DIGITAL CONVERTER (ADC) ADC Control register (ADCON) TIMERS/COUNTERS Timer 0 and Timer 1 Timer T2 Capture and Compare Logic Watchdog Timer (T3) SERIAL I/O PORT: SIO0 (UART) SERIAL I/O PORT: SIO1 (CAN) On-chip CAN-controller CAN Features Interface between CPU and CAN H.
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