PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex®-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. PSoC™ 4100S Plus.
• Automotive Electronics Council (AEC) AEC-Q100 Qualified
• 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine
• Programmable analog - Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode. - 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging - Single-slope 10-bit ADC function provided by a capacitance sensing bloc.
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