x8 A0-A12 Row Add.
• VDD and VDDQ: 2.5V ± 0.2V (-5, -6)
• VDD and VDDQ: 2.5V ± 0.1V (-4)
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
•.
Distributor | Stock | Price | Buy |
---|
No. | Part # | Manufacture | Description | Datasheet |
---|---|---|---|---|
1 | IS46R86400D |
Integrated Silicon Solution |
16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM | |
2 | IS46R83200B |
ISSI |
256Mb DDR Synchronous DRAM | |
3 | IS46R16160B |
ISSI |
256Mb DDR Synchronous DRAM | |
4 | IS46R16160D |
ISSI |
DDR SDRAM | |
5 | IS46R16160F |
Integrated Silicon Solution |
256Mb DDR SDRAM |