S26KL128S 128Mb (16MB) HYPER FLASH

S26KL128S 128Mb (16MB) HYPER FLASH

........................................................................................................................5 1.1 DDR center aligned read strobe (DCARS) functionality ........................................................................................7 1.2 Error detection and correct.

Features

• 3.0 V I/O, 11 bus signals - Single ended clock
• 1.8 V I/O, 12 bus signals - Differential clock (CK, CK#)
• Chip Select (CS#)
• 8-bit data bus (DQ[7:0])
• Read-write data strobe (RWDS) - HYPERFLASH™ memories use RWDS only as a Read Data Strobe
• Up to 333-MBps sustained read throughput
• DDR: two data transfers per clock
• 166-MHz clock rate (333 MBps) at 1.8 V VCC
• 100-MHz clock rate (200 MBps) at 3.0 V VCC
• 96-ns initial random read access time - Initial random access read latency: 5 to 16 clock cycles
• Sequential burst transactions
• Configurable burst characteristics - Wrapped burst l.