DM7474N Dual Positive-Edge-Triggered D-Type Flip-Flop

DM7474N Dual Positive-Edge-Triggered D-Type Flip-Flop

This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transiti.

Features

ircuit (SOIC), JEDEC MS-012, 0.150" Narrow DM7474N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q Q L H X X H L H L X X L H L L X X H H (Note 1) (Note 1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level ↑ = Positive-going transition of the clock. Q0 = The output logic level of Q befor.