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CY8C4A45AZI-483

Cypress
Part Number CY8C4A45AZI-483
Manufacturer Cypress
Description Programmable System-on-Chip
Published Aug 28, 2020
Detailed Description PSoC® Analog Coprocessor: CY8C4Axx Family Datasheet Programmable System-on-Chip (PSoC®) General Description Cypress' PS...
Datasheet PDF File CY8C4A45AZI-483 PDF File

CY8C4A45AZI-483
CY8C4A45AZI-483


Overview
PSoC® Analog Coprocessor: CY8C4Axx Family Datasheet Programmable System-on-Chip (PSoC®) General Description Cypress' PSoC® Analog Coprocessor is a scalable and reconfigurable platform architecture of programmable analog coprocessors that simplify designing embedded systems with multiple sensors.
The PSoC Analog Coprocessor device combines PSoC's flexible Analog Front Ends, programmable analog filters, and high-resolution analog-to-digital converters along with an efficient yet powerful 32-bit Arm® Cortex®-M0+ based signal processing engine – enabling host processors to easily fetch aggregated, pre-processed, and formatted complex sensor data over serial communication interfaces.
Features Programmable Analog Blocks ■ A switched-capacitor Universal Analog Block (UAB) program- mable via PSoC Creator as a second-order analog filter, a 12-bit Incremental Delta-Sigma ADC, or two 13-bit Voltage DACs ■ Two dedicated analog-to-digital converters (ADC) including a 12-bit SAR ADC and a 10-bit single-slope ADC ■ Four opamps, two low-power comparators, and a flexible 38-channel analog mux to create custom Analog Front Ends (AFE) ■ Two 7-bit Current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin CapSense® Capacitive Sensing ■ Cypress's fourth-generation CapSense Sigma-Delta (CSD) providing best-in-class signal-to-noise ratio (SNR) and water tolerance ■ Cypress-supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning (SmartSense™) Segment LCD Drive ■ LCD drive supported on all pins (common or segment) ■ Operates in Deep-Sleep mode with four bits per pin memory Programmable Digital Peripherals ■ Three independent serial communication blocks (SCBs) that are run-time configurable as I2C, SPI or UART ■ Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks with center-aligned, edge, and pseudo-random modes 32-bit Signal Processing Engine ■ Arm Cortex-M0+ CPU up to 48 MHz ■ Up to 32 KB of flash with read acc...



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