DSSHA1 Maxim Integrated Memory-Mapped SHA-1 Coprocessor Datasheet. Stock, Price

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DSSHA1

Maxim Integrated
DSSHA1
DSSHA1 DSSHA1
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Part Number DSSHA1
Manufacturer Maxim Integrated (https://www.analog.com/)
Description The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to per...
Features ♦ SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz) ♦ Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process) ♦ Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs ♦ 64-Byte RAM for Message Input ♦ Five 32-Bit Registers to Read MAC Result ♦ Available in Synthesizable Verilog® ♦ Made as a Low-Level Module to be Instantiated by a Top-Level Module ♦ Includes Test Bench Typical Operating Circuit MICROPROCESSOR ASIC—TOP-LEVEL MODULE DSSHA1 MODULE DESIGN MODULE DS1WM MODULE 3.3V R DS28E01-100 Verilog is a registered trademark of Gatewa...

Document Datasheet DSSHA1 Data Sheet
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