S7R641884M Datasheet

S7R641884M 2Mx36 & 4Mx18 & 8Mx9 Quadruple-II BL4 SRAM

The S7R643684M, S7R641884M and S7R640984M are 75,497,472-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for S7R643684M, 4,194,304 words by 18bits for S7R641884M and 8,388,608 words by 9bits for S7R640984M. The Quadruple operation is possible by supp.

Features

• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future fre- quency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
• Separate independent read and write data ports with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR (Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to re.