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SLG74190

Silego
Part Number SLG74190
Manufacturer Silego
Description 1 to 19 Differential Clock Buffer
Published Sep 15, 2018
Detailed Description Features • Intel DB1900Z Clock Specification Revision 1.0 • 1:19 Differential Zero Delay Buffer • PCIe Gen 2/Gen3 & Inte...
Datasheet PDF File SLG74190 PDF File

SLG74190
SLG74190


Overview
Features • Intel DB1900Z Clock Specification Revision 1.
0 • 1:19 Differential Zero Delay Buffer • PCIe Gen 2/Gen3 & Intel ® QPI • 100ps Input to Output Delay • HCSL Output Buffer • Configuration PLL (ZDB) and Bypass Mode • Programmable PLL Bandwidth • 72 pin QFN package (6/6 RoHS Compliant) SLG74190 1 to 19 Differential Clock Buffer Output Summary • 19 - differential clock output pairs @ 0.
7V • 8 - OE# input pins to control output • 1 - differential external feedback output pair SMBus Address Table SA_1 L L L M M M H H H SA_0 L M H L M H L M H SMBus Address D8 DA DE C2 C4 C6 CA CC CE Note: SA_1 & SA_0 have an integrated pull-down resistor @100kΩ Pin Configuration (Top View) DIF_18# DIF_18 DIF_17# DIF_17 VDD DIF_16# DIF_16 DIF_15# DIF_15 GND DIF_14# DIF_14 DIF_13# DIF_13 VDD OE_12# DIF_12# DIF_12 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDDA GNDA IREF *100M_133M# HBW_BYPASS_LBW# PWRGD/PWRDN# GND VDD CLK_IN CLK_IN# ^SA_0 SDA SCL ^SA_1 FB_IN ...


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