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MxL7704

MaxLinear
Part Number MxL7704
Manufacturer MaxLinear
Description Five Output Universal PMIC
Published Sep 1, 2018
Detailed Description Data Sheet MxL7704 Five Output Universal PMIC General Description Features The MxL7704 is a five output Universal PMI...
Datasheet PDF File MxL7704 PDF File

MxL7704
MxL7704


Overview
Data Sheet MxL7704 Five Output Universal PMIC General Description Features The MxL7704 is a five output Universal PMIC optimized for powering low power FPGAs, DSPs, and microprocessors from 5V inputs.
Four synchronous step down buck regulators range from 1.
5A system power to 4A core power.
A 100mA LDO provides a clean 1.
5V to 3.
6V power for auxiliary devices.
All outputs support ±10% margining and the two highest power outputs support dynamic voltage control to support processors that can utilize this function to save power.
Through a 400kHz I2C interface, the customer can monitor an input voltage flag and PGOOD flags for each output.
The I2C port can also be used to modify power up and down sequencing options, assign PGOOD outputs to the PGOOD pins, enable outputs and select switching frequency.
High switching frequency and a current mode architecture with internal compensation enable a very fast transient response to line and load changes without sacrificing stability and keeping board space to a minimum.
Fault protection features include input undervoltage lockout, overcurrent protection, and thermal protection.
The MxL7704 is offered in a 5mm x 5mm QFN package.
Two pre-programmed standard products are available.
The MxL7704-X has been optimized for powering the Xilinx® Zynq® Ultrascale+™ ZU2 and ZU3 MPSoCs.
The bucks are pre-programmed to provide the core rail (0.
85V up to 4A), DDR3L memory power (1.
35V), I/O and system power (1.
8V and 3.
3V).
Sequencing is tailored to the unique needs of the ZU2 and ZU3 MPSoCs, offering accelerated time to market with Xilinx® Zynq® Ultrascale+™ ZU2 and ZU3 devices.
The MxL7704-A is designed to power a wide range of ARM® Cortex®based processors (A7, A9, and A53) which use a more conventional sequencing scheme where the I/O rails power up first and core is last.
The bucks provide the 1.
2V core rail, 1.
35V DDR3L power, 1.
8V and 3.
3V rails for I/O and system power.
VTT is supported by the addition of the XRP2997 DDR Bus Terminati...


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