A3P400 ProASIC3 Flash Family FPGAs

A3P400 ProASIC3 Flash Family FPGAs

Revision 13 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Features and Benefits High Capacity • 15 k to 1 M System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Instan.

Features

High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI† In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532
  –compliant)†
• FlashLock® to Secure FPGA Contents Low Powe.