CY7C1317BV18 |
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| Part Number | CY7C1317BV18 |
| Manufacturer | Cypress Semiconductor |
| Description | • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 60... |
| Features |
Functional Description
• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive... |
| Document |
 CY7C1317BV18 Data Sheet
PDF 447.88KB |
| Distributor | Stock | Price | Buy |
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18-Mbit QDR II SRAM Two-Word Burst Architecture |
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