GS8342D11BD 36Mb SigmaQuad-II+ Burst of 4 SRAM

GS8342D11BD 36Mb SigmaQuad-II+ Burst of 4 SRAM

Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low NW0–NW1 Synchronous Nybble Writes Input Active Low (x8 only) K Input Clock Inpu.

Features

• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) intputs
• 1.8 V +100/
  –100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pit.