Quad D-Type Flip-Flop - Toshiba
Description
TC74VHC175F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC175F, TC74VHC175FT, TC74VHC175FK
Quad D-Type Flip Flop with Clear
The TC74VHC175 is an advanced high speed CMOS QUAD D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
These four flip-flops are controlled by a clock input (CK) and a clear input ( CLR ).
The information data applied to the D inputs (D1 thru D4) are transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the positive-going edge of the clock pulse.
When the CLR input is held low, the Q outputs are at the low logic level and the Q outputs are at the high logic level, regardless of other input conditions.
An input protection circuit ensures that 0 to 5.
5 V can be applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
Features
• High speed: fmax = 210 MHz (typ.
) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.
5 V • Low noise: VOLP = 0.
8 V (max) • Pin and function compatible with 74ALS175
TC74VHC175F TC74VHC175FT TC74VHC175FK
Weight SOP16-P-300-1.
27A TSSOP16-P-0044-0.
65A VSSOP16-P-0030-0.
50
: 0.
18 g (typ.
) : 0.
06 g (typ.
) : 0.
02 g (typ.
)
Start of commercial production
1991-11
1
2014-03-01
Pin Assignment
TC74VHC175F/FT/FK
IEC Logic Symbol
CLR 1 Q1 2 Q1 3 D1 4 D2 5 Q2 6 Q2 7
GND 8
(top view)
16 VCC 15 Q4 14 Q4 13 D4 12 D3 11 Q3 10 Q3 9 CK
Truth Table
Inputs
CLR D CK
L
X
X
H
L
H
H
H
X
X: Don’t care
Outputs
Q
Q
L
H
L
H
H
L
Qn Qn
Function
Cle...
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