4M SRAM
Description
R1LP0408C-C Series
4 M SRAM (512-kword × 8-bit)
REJ03C0077-0100Z Rev.
1.
00 Aug.
01.
2003
Description
The R1LP0408C-C is a 4-Mbit static RAM organized 512-kword × 8-bit.
R1LP0408C-C Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell).
The R1LP0408C-C Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems.
It has packaged in 32-pin SOP, 32-pin TSOP II.
Features
• Single 5 V supply: 5 V ± 10% • Access time: 55/70 ns (max) • Power dissipation: Active: 10 mW/MHz (typ) Standby: 4 µW (typ) • Completely static memory.
No clock or timing strobe required • Equal access and cycle times • Common data input and output.
Three state output • Directly TTL compatible.
All inputs and outputs • Battery backup operation.
• Operating temperature: −20 to +70°C
Rev.
1.
00, Aug.
01.
2003, page 1 of 13
R1LP0408C-C Series
Ordering Information
Type No.
R1LP0408CSP-5SC R1LP0408CSP-7LC R1LP0408CSB-5SC R1LP0408CSB-7LC R1LP0408CSC-5SC R1LP0408CSC-7LC Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 400-mil 32-pin plastic TSOP II reverse (32P3Y-J) 400-mil 32-pin plastic TSOP II (32P3Y-H) Package 525-mil 32-pin plastic SOP (32P2M-A)
Rev.
1.
00, Aug.
01.
2003, page 2 of 13
R1LP0408C-C Series
Pin Arrangement
32-pin SOP 32-pin TSOP
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 VCC A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3
32-pin TSOP (reverse)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
Pin Description
Pin name A0 to A18 I/O0 to I/O7 CS# (CS) OE# (OE) WE# (WE) VCC VSS Function Address input Data input/output Chip select Output enable Write enable ...
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