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NT16TC72C4NB1NL

Nanya Technology

Registered DDR3 SDRAM DIMM


NT16TC72C4NB1NL
NT16TC72C4NB1NL

PDF File NT16TC72C4NB1NL PDF File


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NT2GC72B89B0NJ/NT2GC72B89B2NJ/NT2GC72C89B0NJ/NT2GC72C89B2NJ NT4GC72B4PB0NL/NT4GC72C4PB0NL/NT4GC72C4PB2NL/NT4GC72B8PB0NL/NT4GC72C8PB0NL/NT4GC72C8PB2NL NT8GC72B4NB1NJ/NT8GC72B4NB3NJ/NT8GC72C4NB1NJ/NT8GC72C4NB3NJ NT16TC72B4NB1NL/NT16TC72C4NB1NL/NT16TC72C4NB3NL 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 / 16GB: 2G x 72 PC3-8500 / PC3-10600 Registered DDR3 SDRAM DIMM Based on DDR3-1066/1333 256Mx8 (2GB/4GB) / 512Mx4 (4GB/8GB) SDRAM B-Die Based on DDR3-1066 1Gx4 (DDP) (16GB) SDRAM B-Die Features •Performance: Speed Sort DIMM CAS Latency fck – Clock Frequency tck – Clock Cycle fDQ – DQ Burst Frequency PC3-8500 -BE 7 533 1.
875 1066 PC3-10600 -CG 9 667 1.
5 1333 MHz ns Mbps • Programmable Operation: - DIMM  Latency: 6,7,8,9 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write • Two different termination values (Rtt_Nom & Rtt_WR) • 15/10/1 (row/column/rank) Addressing for 2GB • 15/11/1 (row/column/rank) Addressing for 4GB (512Mx4 Device) • 15/10/2 (row/column/rank) Addressing for 4GB (256Mx8 Device) • 15/11/2 (row/column/rank) Addressing for 8GB • 15/11/4 (row/column/rank) Addressing for 16GB • Extended operating temperature rage • Auto Self-Refresh option • Serial Presence Detect • Gold contacts • SDRAMs are in 78-ball BGA Package • RoHS compliance and Halogen free Unit • 240-Pin Registered Dual In-Line Memory Module (RDIMM) • 2GB/4GB: 256Mx72/512Mx72 DDR3 Registered DIMM based on 256Mx8 DDR3 SDRAM B-Die devices • 4GB/8GB: 512Mx72/1024Mx72 DDR3 Registered DIMM based on 512Mx4 DDR3 SDRAM B-Die devices • 16GB: 2Gx72 DDR3 Registered DIMM based on 1024Mx4 (DDP) DDR3 SDRAM B-Die devices • Intended for 533MHz/667MHz applications • Inputs and outputs are SSTL-15 compatible •VDD = VDDQ = 1.
5V ± 0.
075V (for DDR3) •VDD = VDDQ = 1.
35V -0.
0675/+0.
1V (for DDR3L) • SDRAMs have 8 internal banks for concurrent operation • Differential clock inputs • Data is read or written on both clock edges • DRAM DLL aligns DQ and DQS transitions with...



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