Synchronous SRAM
Description
COTS PEM SSRAM AS5SP256K36
9.0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
FEATURES Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support ...
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