256K X 8 BIT LOW VOLTAGE CMOS SRAM - AMIC Technology
Description
LP62S2048-I Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.
7V to 3.
3V n Access times: 70/100 ns (max.
) n Current: Low power version: Operating: 30mA (max.
) Standby: 50µA (max.
) Very low power version: Operating: 30mA (max.
) Standby: 10µA (max.
) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.
) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.
4mm) and 36-pin CSP packages
General Description
The LP62S2048-I is a low operating current 2,097,152-bit static random access memory organized as 262,144 words by 8 bits and operates on a low power supply range: 2.
7V to 3.
3V.
It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.
Data retention is guaranteed at a power supply voltage as low as 2V.
Pin Configurations
n SOP n TSOP/(TSSOP) n CSP (Chip Size Package) 36-pin Top View
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 32 31 30 29 28 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 17 32 H A9 A10 A11 A12 A13 A14 1 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC GND NC OE CE1 A17 A16 A15 I/O3 I/O4 16 1
LP62S2048V-I (LP62S2048X-I)
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
A B C D E F G
A0 I/O5 I/O6 GND VCC I/O7 I/O8
(August, 2001, Version 1.
0)
LP62S2048M-I
Pin No.
Pin Name Pin No.
Pin Name
1 A11 17 A3
2 A9 18 A2
3 A8 19 A1
4 A13 20 A0
5 WE 21 I/O1
6 CE2 22 I/O2
7 A15 23 I/O3
8 VCC 24 GND
9 A17 25 I/O4
10 A16 26 I/O5
11 A14 27 I/O6
12 A12 28 I/O7
13 A7 29 I/O8
14 A6 30 CE1
15 A5 31 A10
16 A4 32 OE
1
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