LOW SKEW CLOCK INVERTER AND DIVIDER
Description
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LOW SKEW CLOCK INVERTER AND DIVIDER Description
The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
Using our patented Phase-Locked Loop (PLL) techniques, the device operates from a frequency range of 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode.
In applications that need to maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) modes should be used.
This chip is not a zero delay buffer.
Many applications may be able to use the ICS527 for zero delay dividers.
ICS548A-03
Features
• • • • • •
Packaged in 16-pin SOIC (150 mil) Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew (500 ps) on CLK, CLK, and CLK/2 All outputs can be tri-stated Entire chip can be powered down by changing one or two select pins
• 3.
3 V operating range • Available in commercial and industrial temperature
ranges
• RoHS 5 (green) or RoHS 6 (green and lead free)
compliant package
Block Diagram
VDD GND
2
2
CLK
S3:S0
4
Clock input
Input Buffer
Clock Synthesis and Divider Circuitry
CLK CLK/2
OE (all outputs)
IDT™ / ICS™ LOW SKEW CLOCK INVERTER AND DIVIDER
1
ICS548A-03
REV C 063006
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER
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CLOCK DIVIDER
Pin Assignment
ICLK VDD VDD S3 GND GND S2 S0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DC DC DC CLK CLK CLK/2 OE S1
CLK, CLK, and CLK/2 Select Table (MHz)
S3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
S0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CLK, CLK
Low Input/4 Input Input/2 Low Input x 2 Input/5 Input/3 Low Input/4 Input Input/2 Low Input/6 Input/8 Input/2
CLK/2
Low Input/8 Input/2 Input/4 Low Input Input/10 Input/6 Low Input/8 Input/2 Input/4 Low Input/12 Input/16 Input/4
PLL
OFF ON ON ON OFF ON ON ON OFF ON ON O...
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