200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter
Description
10-Bit, 200 MSPS/250 MSPS 1.
8 V Analog-to-Digital Converter AD9601
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SNR = 59.
4 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 9.
7 @ fIN up to 70 MHz @ 250 MSPS (−1.
0 dBFS) SFDR = 81 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.
0 dBFS) Excellent linearity DNL = 0.
2 LSB typical INL = 0.
2 LSB typical CMOS outputs Single data port at up to 250 MHz Demultiplexed dual port at up to 2 × 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 274 mW @ 200 MSPS 322 mW @ 250 MSPS Programmable input voltage range 1.
0 V to 1.
5 V, 1.
25 V nominal 1.
8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN AGND AVDD (1.
8V)
REFERENCE CML VIN+ VIN– TRACK-AND-HOLD ADC 10-BIT CORE CLK+ CLK– CLOCK MANAGEMENT 10
AD9601
DRVDD DRGND
OUTPUT 10 STAGING LVDS
Dx9 TO Dx0
OVRA OVRB SERIAL PORT DCO+
07100-001
DCO– RESET SCLK SDIO CSB
Figure 1.
GENERAL DESCRIPTION
The AD9601 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use.
The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems.
All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.
The ADC requires a 1.
8 V analog voltage supply and a differential clock for full performance operation.
The digital outputs are CMOS compatible and support either twos complement, offset binary format, or Gray code.
A data clock output is available for proper output...
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