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PLL103-04

1-to-4 Clock Distribution Buffer

Description

Preliminary PLL103-04 1-to-4 Clock Distribution Buffer FEATURES 4 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. Output enable mode available to tri-state all outputs. www.DataSheet4U.com 3.3V operation. Available in 8-P...

PhaseLink Corporation

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