(AL4CAxx) 512/ 1K/ 2K/ 4K/ 8K x 9 Asynchronous FIFOs
Description
AL4CA01/02/03/04/05
512/ 1K/ 2K/ 4K/ 8K x 9 Asynchronous FIFOs
Applications
- ATM switches - Routers - Cable modems - Wireless base stations www.
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com - SONET(Synchronous Optical Network) multiplexers - Multimedia systems - TBC(Time Base Corrector) - Hard Disk cache memory - Buffer for Communications
Features
• • • • • • • • • • • • • High performance, low-power, FIFO(FirstIn First-Out) memory 512 x9 bit I/O port (AL4CA01) 1K x9 bit I/O port (AL4CA02) 2K x9 bit I/O port (AL4CA03) 4K x9 bit I/O port (AL4CA04) 8K x9 bit I/O port (AL4CA05) Asynchronous 12ns access time Fully independent input/output port access Empty, Full, Half Full flags Auto Retransmit Cascadable expansion in depth and width 3.
3-volt power tolerant of 5-volt input Standard 32-pin PLCC,
Description
The AL4CA01/02/03/04/05 Asynchronous FIFO (First In First Out) memory provides completely independent 9bit bus width input and output port control that have a maximum data access time as fast as 12ns.
The products are available in densities from 4Kbit to 64Kbit with word depths from 512bit to 8Kbit.
Ordering Information
Part number Package Power Supply AL4CA01, AL4CA02, AL4CA03, AL4CA04, AL4CA05 32-pin plastic PLCC +3.
3V±10%
13
5
14
AVERLOGIC
AL4CA0X X-XX-XX XXXXX XXXX
4
1
20
30
21 PLCC TOP VIEW
29
Input data bus
Input Buffer
Memory Array 512 x9, 1K x9, 2K x9, 4K x9, 8K x9, 16K x9,
Output Buffer
Output data bus
/W
Write Control Logic Write Pointer
Read Control Logic Read Pointer
/R
/FF Offset Regissers Flag Logic /EF
/RS
Expansion Logic Reset Logic
/XO /XI(/HF)
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/FL(RT/)
AL4CA0x FIFO Block Diagram
The read and write operations are internally sequential through the managing of address pointers, with no address line control required to store and retrieve data.
Data is toggled in and out of the FIFO through the use of the Write and Read enable pins.
Additional features of the AL4CA0x series include: Retransmit(/RT) that allows for reset of the read po...
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