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ICS951901

ICS

Programmable Frequency Generator & Integrated Buffers

ICS951901
ICS951901

PDF File ICS951901 PDF File

Description
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ICS951901 Programmable Frequency Generator & Integrated Buffers for Pentium III Processor Recommended Application: Single chip clock solution for IA platform.
Output Features: • 3 - CPU @ 2.
5V • 13 - SDRAM @ 3.
3V • 6 - PCI @3.
3V, • 2 - AGP @ 3.
3V • 1 - 48MHz, @3.
3V fixed.
• 1 - 24/48MHz, @3.
3V selectable by I2C (Default is 24MHz) • 2 - REF @3.
3V, 14.
318MHz.
Features: • Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable SDRAM and CPU skew.
• Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage.
• Watchdog timer technology to reset system if over-clocking causes malfunction.
• Uses external 14.
318MHz crystal.
• FS pins for frequency select Skew Specifications: • CPU - CPU: < 175ps • SDRAM - SDRAM < 250ps (except SDRAM12) • PCI - PCI: < 500ps • CPU (early) - PCI: 1-4ns (typ.
2ns) Pin Configuration VDDA *(AGPSEL)REF0 1 *(FS3)REF1 GND X1 X2 VDDPCI *(FS1)PCICLK_F *(FS2)PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 GND VDDAGP AGPCLK0 AGPCLK1 GND GND *(FS0)48MHz *(MODE)24_48MHz VDD48 SDATA SCLK 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL CPUCLK0 CPUCLK1 CPUCLK2 GND VDDSDR SDRAM0 SDRAM1 SDRAM2 GND SDRAM3 SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND SDRAM8/PD# SDRAM9/SDRAM_STOP# GND SDRAM10/PCI_STOP# SDRAM11/CPU_STOP# SDRAM12 VDDSDR 48-Pin 300mil SSOP * These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz Functionality Bit2 FS3 Bit7 FS2 Bit6 FS1 Bit5 FS0 Bit4 CPU MHz SDRAM MHz PCI MHz AGP1 SEL=1 AGP0 SEL=0 2 REF(1:0) CPU DIVDER Stop 3 CPUCLK (2:0) SDRAM DIVDER Stop 13 SDRAM (12:0) SDATA SCLK FS(3:0) PD# PCI_STOP# CPU_STOP# SDRAM_STOP# MODE AGP_SEL Control Logic PCI DIVDER Stop 5 PCICLK (4:0) PCICLK_F AGP DIVDER Config.
Reg.
2 AGP (1:0) 0 0 0 0 0 0 0 ...


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