CMOS / SNOS NVSRAM
Description
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P10C68/P11C68
PRELIMINARY INFORMATION
DS3600-1.
2 September 1992
P10C68/P11C68
(Previously PNC10C68 and PNC11C68)
CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
(Supersedes DS3159-1.
3, DS3160-1.
3, DS3234-1.
1, DS3235-1.
1)
The P10C68 and P11C68 are fast static RAMs (35 and 45 ns) with a non-volatile electically-erasable PROM (EEPROM) cell incorporating in each static memory cell.
The SRAM can be read and written an unlimited number of times while independent non-volatile data resides in PROM.
On the P10C68 data may easily be transferred from the SRAM to the EEPROM (STORE) and from the EEPROM back to the SRAM ( RECALL) using the NE (bar) pin.
The Store and Recall cycles are initiated through software sequences on the P11C68.
These devices combine the high performance and ease of use of a fast SRAM with the data integrity of nonvolatility.
The P10C68 and P11C68 feature the industry standard pinout for non-volatile RAMs in a 28-pin 0.
3-inch plastic and ceramic dual-in-line packages.
NE A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W NC A8 A9 A 11 G A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3
FEATURES I Non-Volatile Data Integrity I 10 year Data Retention in EEPROM I 35ns and 45ns Address and Chip Enable Access Times I 20ns and 25ns Output Enable Access I Unlimited Read and Write to SRAM I Unlimited Recall Cycles from EEPROM I 104 Store Cycles to EEPROM I Automatic Recall on Power up I Automatic Store Timing I Hardware Store Protection I Single 5V ± 10% Operation I Available in Standard Package 28-pin 0.
3-inch DIL plastic and ceramic I Commercial and Industrial temperature ranges ORDERING INFORMATION (See back page) Pin Name A0 - A12 W DQ0 - DQ7 E G VCC VSS Pin 1 NE Pin 1 N/C Function Address inputs Write enable Data in/out Chip enable Output enable Power (+5V) Ground Non volatile enable P10C68 No connection P11C68
Figure 1.
Pin connections - top view.
1
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