Serial ATA/Fibre Channel Clock Synthesizer
Description
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ICS426
Serial ATA/Fibre Channel Clock Synthesizer
Features
• • • • • • •
Packaged in 16 pin TSSOP Input crystal or clock frequency of 25 MHz (typical) Supports serial ATA Generation 1 Supports Fiber Channel Duty cycle of 45/55 Operating voltage of 3.
3V Advanced, low power, CMOS process
Description
The ICS426 was developed for serial ATA (SATA) and fiber channel.
It generates a high quality, high frequency clock output from a low cost frequency crystal or clock input.
Using Phase-Locked-Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal or clock input.
Block Diagram
VDD
4
S0:S1 X1 Crystal Oscillator X2
25 MHz Crystal or Clock Input
PLL /Clock Synthesis Circuitry
CLK
Capacitors may be required with a crystal input.
6
GND
OE
MDS 426 B Integrated Circuit Systems, Inc.
q
1
525 Race Street, San Jose, CA 95126
q
Revision 091102 tel (408) 295-9800
q
www.
icst.
com
ICS426 Serial ATA/Fibre Channel Clock Synthesizer
Pin Assignment
X1/ICLK VDD VDD GND GND S1 VDD CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 GND GND OE GND S0 VDD GND
Clock Output Select Table (MHz)
S1
0 0 1 1
S0
0 1 0 1
Input 25 25 25 25
CLK Output 75 150 106.
25 156.
25
16 pin 173 mil (0.
65 mm) TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X1/ICLK VDD VDD GND GND S1 VDD CLK GND VDD S0 GND OE GND GND X2
Pin Type
XI Power Power Power Power Input Power Output Power Power Input Power Input
Power
Pin Description
Crystal connection.
Connect to a 25 MHz fundamental mode crystal or clock input.
Connect to +3.
3 V.
Connect to +3.
3 V.
Connect to ground.
Connect to ground.
Select pin 1 determines CLK output based on table above.
Internal pull-up.
Connect to +3.
3 V.
Clock output.
Tri-state output when OE is low.
Connect to ground.
Connect to +3.
3V.
Select pin 0 determines CLK output based on table above.
Internal pull-up.
Connect to ground.
Output Enable.
All outputs are tri-stated when low.
Internal pull...
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