(M68HCx05BDx) High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
Description
MC68HC05BD3D/H
MC68HC05BD3 TECHNICAL DATA
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MC68HC05BD3 MC68HC705BD3 MC68HC05BD5
TECHNICAL DATA
GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3
TPG MC68HC05BD5
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GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5
TPG
MC68HC05BD3 MC68HC705BD3 MC68HC05BD5
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
TPG
Conventions
Register and bit mnemonics are defined in the paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ‘u’ is used to indicate an undefined state (on reset).
TPG
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