1 MEG x 4 DRAM Fast Page Mode DRAM
Description
DRAM
Austin Semiconductor, Inc.
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY SPECIFICATIONS
• SMD 5962-90847 • MIL-STD-883
DQ1 DQ2 WE\ RAS\ A9 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10
20-Pin DIP (C, CN)
MT4C4001J
PIN ASSIGNMENT (Top View)
20 19 18 17 16 15 14 13 12 11 Vss DQ4 DQ3 CAS\ OE\ A8 A7 A6 A5 A4
20-Pin SOJ (ECJ), 20-Pin LCC (ECN), & 20-Pin Gull Wing (ECG)
DQ1 DQ2 WE\ RAS\ A9 1 2 3 4 5 26 25 24 23 22 Vss DQ4 DQ3 CAS\ OE\
FEATURES
• Industry standard x4 pinout, timing, functions, and packages • High-performance, CMOS silicon-gate process • Single +5V±10% power supply • Low-power, 2.
5mW standby; 300mW active, typical • All inputs, outputs, and clocks are fully TTL and CMOS compatible • 1,024-cycle refresh distributed across 16ms • Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR), and HIDDEN • FAST PAGE MODE access cycle • CBR with WE\ a HIGH (JEDEC test mode capable via WCBR)
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A0 A1 A2 A3 Vcc
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
20-Pin DIP (CZ) OE\ 1 DQ3 3 Vss 5 2 CAS\ 4 DQ4 6 DQ1 8 WE\ 10 A9 12 A1 14 A3 16 A4 18 A6 20 A8
DQ2 7 RAS\ 9
A0 11 A2 13 Vcc 15 A5 17 A7 19
OPTIONS
• Timing 70ns access 80ns access 100ns access 120ns access • Packages Ceramic DIP (300 mil) Ceramic DIP (400 mil) Ceramic LCC* Ceramic ZIP Ceramic SOJ Ceramic Gull Wing
MARKING
-7 -8 -10 -12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration.
During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time.
RAS\ is used to latch the first 10 bits and CAS\ the later 10 bits.
A READ or WRITE cycle is selected with the WE\ input.
A logic HIGH on WE\ dictates READ mode while a logic LOW on WE\ dictates WRITE mode.
During a WRITE cycle, data-in (D) is latched by the falling edge of WE\ or CAS\, whichever occurs last.
If WE\ goes LOW prior to CAS\ going LOW, the output pin(s) remain open (High-Z) until the ...
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