1:4 LVPECL Fanout Buffer/Translator - Micrel Semiconductor
Description
SY89854U
Precision Low Power 1:4 LVPECL Fanout Buffer/Translator with Internal Termination
General Description
The SY89854U is a 2.
5V/3.
3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer.
Optimized to provide four identical output copies with less than 20ps of skew and less than 10ps(pp) total jitter, the SY89854U can process clock signals as fast as 2GHz.
The differential input includes Micrel’s unique, patent pending 3-pin input termination architecture that interfaces to any differential signal (AC or DCcoupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path.
For AC-coupled input interface applications, an on-board output reference voltage (VREF-AC) is provided to bias the center-tap (VT) pin.
The outputs are 800mV LVPECL, with fast rise/fall times guaranteed to be less than 180ps.
The SY89854U operates from a 2.
5V ±5% supply or a 3.
3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C.
The SY89854U is part of Micrel’s high-speed, Precision Edge® product line.
All support documentation can be found on Micrel’s web site at: www.
micrel.
com.
Typical Applications
200MHz (Q - /Q)
Features
Precision Edge®
• Precision 1:4, LVPECL fanout buffer
• Low power: 137mW (2.
5V typ)
• Guaranteed AC performance over temperature and supply voltage: – DC- to > 2GHz Clock fMAX – <340ps tpd – <180ps tr/tf time – <20ps max.
skew
• Ultra-low jitter design: – <1ps(rms) random jitter – <10ps(pp) deterministic jitter – <10ps(pp) total jitter (clock)
• Unique patent pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS)
• Typical 800mV (100k) LVPECL output swing
• Power supply 2.
5V ±5% or 3.
3V ±10%
• Industrial temperature range –40°C to +85°C
• Available in ultra-small (3mm x 3mm) 16-pin QFN package
Applications
• SONET and All GigE clock distribution • Fibre Channel clock and data distribution • Backplane distribution
Output S...
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