9-Mbit Burst of Two Pipelined SRAMs
Description
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PREMILINARY
CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
Separate independent Read and Write data ports — Supports concurrent transactions 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time 2-word burst on all accesses Double Data Rate (DDR) interfaces on both Read and Write...
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