CMOS DRAM
Description
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Description
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.
3V only power supply.
Low voltage operation is more suitable to be used on battery backup, portable electronic application.
Selfrefresh is supported and CBR cycles are being performed.
lt is packaged in JEDEC standard 42-pin 400mil SOJ and 50(44)-pin 400mil TSOPII.
Features
• Single 5V or 3.
3V only power supply • High speed tRAC access time: 50/60ns • Extended-data-out (EDO) page mode access • I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.
3V) • 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh • Refresh interval: - RAS only refresh, CAS - before - RAS refresh and hidden refresh: 1024 cycles in 16 ms - Self-refresh: 1024 cycles • JEDEC standard pinout: 44-pin 400mil SOJ and 50(44)-pin 400mil TSOPII
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Document:1G5-0179 Rev.
2 Page 1
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Pin Configuration 42-Pin 400mil SOJ VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
50(44)-Pin 400mil TSOPII
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS
1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26
GND DQ15 DQ14 DQ13 DQ12 GND DQ11 DQ10 DQ9 DQ8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
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NC NC WE OE RAS A9 NC A8 NC A7 A0 A1 A6 DataSheet4U.
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Pin Description Pin Name A0-A9 Functi...
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