3-to-8 Line Decoder
Description
TC74LVX138F/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LVX138F, TC74LVX138FT
3-to-8 Line Decoder
The TC74LVX138F/ FT is a high-speed CMOS 3-to-8 line decoder fabricated with silicon gate CMOS technology.
Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation.
This device is suitable for low-voltage and battery operated systems.
When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low.
When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high.
G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.
An input protection circuit ensures that 0 to 5.
5V can be applied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
Features
• High-speed: tpd = 5.
5 ns (typ.
) (VCC = 3.
3 V) • Low power dissipation: ICC = 4 μA (max) (Ta = 25°C) • Input voltage level: VIL = 0.
8 V (max) (VCC = 3 V)
VIH = 2.
0 V (min) (VCC = 3 V) • Power-down protection provided on all inputs • Balanced propagation delays: tpLH ∼− tpHL • Pin and function compatible with 74HC138
TC74LVX138F
TC74LVX138FT
Weight SOP16-P-300-1.
27A TSSOP16-P-0044-0.
65A
: 0.
18 g (typ.
) : 0.
06 g (typ.
)
Start of commercial production
1993-01
1
2014-03-01
Pin Assignment (top view)
TC74LVX138F/FT
A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8
16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
IEC Logic Symbol
(1) A
(2) B
(3) C
(6) G1
(4) G2A
(5) G2B
Bin/Oct
(15)
1
0
Y0
(14)
2
1
Y1
(13)
4
2
Y2
(12)
3
Y3
&
(11)
4
Y4
(10)
5
Y5
(9)
EN
6
Y6
(7)
7
Y7
(1) A
(2) B
(3) C
(6) G1
(4) G2A
(5) G2B
Dmux
0
0 G
2
7
&
EN
(15)
0
Y0
(14)
1
Y1
(13)
...
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