CMOS IEEE 1284 Peripheral Controller
Description
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TE6137 (1/3) IL22
C-MOS IEEE 1284 PERIPHERAL CONTROLLER
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42 40 35 30 29
43 45 GND VDD (+5 V)
GND VDD (+5 V)
28
25 GND
50
GND 20 VDD (+5 V) GND GND
GND
55 56
15
10
14
1
5
(VDD = +5 V) PIN No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O O O O I I I I — I/O I/O I/O I/O I/O I/O SIGNAL BPoINT2 BPoINT1 BPoINT0 iA3 iA2 iA1 iA0 GND bD7 bD6 bD5 bD4 bD3 bD2 PIN No.
15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O — — I I — I — I I I I O SIGNAL bD1 bD0 GND VDD iRD/RW iWR/EN GND BPiCLK GND iRST iCIS iCS BPiDAK1 BPoDRQ1 PIN No.
29 30 31 32 33 34 35 36 37 38 39 40 41 42 I/O I I O O I O — — I/O I/O I/O I/O I/O I/O SIGNAL BPiDEND1 BPiDAK0 BPo BPoDEND0 BPiCLS BPoRT VDD GND BPbD7 BPbD6 BPbD5 BPbD4 BPbD3 BPbD2 PIN No.
43 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O I/O I/O — — I I I I O O O O O — SIGNAL BPbD1 BPbD0 GND VDD BPiSEI BPiAF BPiINI BPiSTB BPoPE BPoACK BPoBY BPoFT BPoSE GND
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TE6137 (2/3) INPUT BPiAF BPiCLK BPiCLS BPiDAK0 BPiDAK1 BPiDEND1 BPiINI BPiSEI BPiSTB iA0 - iA3 iCIS iCS iRD/WR iRST iWR/EN OUTPUT BPoACK BPoBY BPoDEND0 BPoDRQ0 BPoDRQ1 BPoFT BPoINT0 BPoINT1 BPoINT2 BPoPE BPoRT BPoSE
: : : : : : : : : : : : : : :
COMPATIBILITY = n AUTO Fd CLOCK COMPATIBILITY MODE LEVEL SELECT DMA ACKNOWLEDGE0 DMA ACKNOWLEDGE1 DMA END1 COMPATIBILITY = n INITIAL COMPATIBILITY = n SELECT IN COMPATIBILITY = n STROBE ADDRESS CPU INTERFACE SELECT CHIP SELECT READ/READ WRITE SELECT RESET WRITE/ENABLE
: : : : : : : : : : : :
COMPATIBILITY = n ACK COMPATIBILITY = BUSY DMA END0 DMA REQUEST0 DMA REQUEST1 COMPATIBILITY = n FAULT INTERRUPT REQUEST0 INTERRUPT REQUEST1 INTERRUPT REQUEST2 COMPATIBILITY = P ERROR INDICATE REVERSE TRANSFER COMPATIBILITY = SELECT
INPUT/OUTPUT bD0 - bD7 : DATA BUS BPbD0 - BPbD7 : COMPATIBILITY = DATA
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TE6137 (3/3)
RAM
JR1LITE ROM CPU I/F REGISTER
CPU
INTERRUPT CONTROL
PROTCOL CONTROL
HOST I/F
DMAC
DMA CONTROL
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