256M bits DDR SDRAM (64M words x 4 bits)
Description
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DATA SHEET
256M bits DDR SDRAM
EDD2504AKTA-E (64M words × 4 bits)
Description
The EDD2504AKTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 4 bits × 4 banks.
Read and write operations are performed at the cross points of the CK and the /CK.
This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
(Top view)
Features
• Power supply : VDDQ = 2.
5V ± 0.
2V : VDD = 2.
5V ± 0.
2V • Data rate: 333Mbps/266Mbps (max.
) • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs, outputs, and DM are synchronized with DQS • 4 internal banks for concurrent operation • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • SSTL_2 compatible I/O • Programmable burst length (BL): 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.
5 • Programmable output driver strength: normal/weak • Refresh cycles: 8192 refresh cycles/64ms 7.
8µs maximum average periodic refresh interval • 2 variations of refresh Auto refresh Self refresh • TSOP ...
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