(MC74HC4049 / MC74HC4050) Hex Buffers/Logic-Level Down Converters
Description
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Buffers/Logic-Level Down Converters
High–Performance Silicon–Gate CMOS
The MC54/74HC4049 consists of six inverting buffers, and the MC54/74HC4050 consists of six noninverting buffers.
They are identical in pinout to the MC14049UB and MC14050B metal–gate CMOS buffers.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The input protection circuitry on these devices has been modified by eliminating the VCC diodes to allow the use of input voltages up to 15 volts.
Thus, the devices may be used as logic–level translators that convert from a high voltage to a low voltage while operating at the low–voltage power supply.
They allow MC14000–series CMOS operating up to 15 volts to be interfaced with High–Speed CMOS at 2 to 6 volts.
The protection diodes to GND are Zener diodes, which protect the inputs from both positive and negative voltage transients.
• • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 5 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No.
7A • Chip Complexity: 36 FETs or 9 Equivalent Gates (4049) 24 FETs or 6 Equivalent Gates (4050)
MC54/74HC4049 MC54/74HC4050
J SUFFIX CERAMIC PACKAGE CASE 620–10
1
16
16 1
N SUFFIX PLASTIC PACKAGE CASE 648–08
16 1
D SUFFIX SOIC PACKAGE CASE 751B–05
ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD Ceramic Plastic SOIC
PIN ASSIGNMENT LOGIC DIAGRAMS HC4049 (INVERTING BUFFER)
A0 2 Y0 VCC Y0 A0 Y1 Y0 A1 Y2 Y1 A2 GND A2 7 6 Y2 A2 7 6 Y2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC Y5 A5 NC Y4 A4 Y3 A3
HC4050 (NONINVERTING BUFFER)
A0 3 2
A1
4
Y1
A1
5
4
NC = NO CONNECTION
A3
9
10
Y3
A3
9
10
Y3
FUNCTION TABLE
A4 11 12 Y4 A4 11 12 Y4 A Input L H Y Outputs HC4049 H L HC4060 L H
A5
14
15
Y5
A5
14
15
Y5
PIN 1 = VCC...
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