DDR 13-Bit to 26-Bit Registered Buffer
Description
Integrated Circuit Systems, Inc.
ICSSSTVF16859
Advance Information
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Applications: • DDR Memory Modules: - DDRI (PC1600, PC2100) - DDR333 (PC2700) - DDRI-400 (PC3200) • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class I specifications on outputs • Low-voltage operation - VDD = 2.
3V to 2.
7V • Available in 64 pin TSSOP and 56 pin MLF packages
Pin Configurations
Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ
Truth Table1
Inputs RESET# L H H H CLK X or Floating ↑ ↑ L or H CLK# X or Floating ↓ ↓ L or H D X or Floating H L X Q Outputs Q L H L Q0(2)
64-Pin TSSOP
6.
10 mm.
Body, 0.
50 mm.
pitch
Q8A VDDQ Q9A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VDD VDDQ D11
56 43
Notes: 1.
H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care Output level before the indicated steady state input conditions were established.
2.
Block Diagram
CLK CLK# RESET# D1 VREF R CLK D1 Q1A Q1B
Q7A 1 Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 14
15
ICSSSTVF16859
42 D10
ICSSSTVF16859
D9 D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 D5 29 D4
28
To 12 Other Channels
0776—03/18/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development.
Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without noti...
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