OCTAL D FLIP-FLOP WITH ENABLE
Description
MC74F377 OCTAL D FLIP-FLOP WITH ENABLE
The MC74F377 is a high-speed 8-Bit Register.
The register consists of eight D-Type Flip-Flops with individual D inputs and Q outputs.
The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is LOW.
This device is supplied in a 20-pin package.
• High Impedance NPN Base Inputs for Reduced Loading (20 µA in • • • • •
HIGH and LOW States) Ideal for Addressable Register Applications Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock See: MC74F373 for Transparent Latch Version MC74F374 for 3-State Version
OCTAL D FLIP-FLOP WITH ENABLE
FAST™ SCHOTTKY TTL
20 1
J SUFFIX CERAMIC CASE 732-03
CONNECTION DIAGRAM (TOP VIEW)
VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11
20 1
N SUFFIX PLASTIC CASE 738-03
20
1 E
2 Q0
3 D0
4 D1
5 Q1
6 Q2
7 D2
8 D3
9 Q3
10 GND
1
DW SUFFIX SOIC CASE 751D-03
ORDERING INFORMATION
MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC
FUNCTION TABLE
Inputs Operating Mode Load “1” Load “0” Hold (do nothing) CP ↑ ↑ ↑ X E l l h H Dn h l X X Outputs Qn H L No Change No Change
H = HIGH voltage level steady state; h = HIGH voltage level one setup time prior to the LOW-to-HIGH Clock transition; L = LOW voltage level steady state; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; X = Don’t Care; ↑ = LOW-to-HIGH clock transition
FAST AND LS TTL DATA 4-278
MC74F377
FUNCTIONAL DESCRIPTION The MC74F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.
The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Enable (E) is LOW.
The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the LOWto-HIGH clock transition for predictable operation...
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