DDR SDRAM Registered Module
Description
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 256Mb E-die (x4, x8) with 1,700 / 1,200mil Height & 72-bit ECC
Revision 1.
4 January, 2004
Revision 1.
4 February, 2004
256MB, 512MB, 1GB Registered DIMM
Revision History
Revision 1.
0 (April, 2003) - First release Revision 1.
1 (July, 2003) - Delete speed B3 Revision 1.
2 (August, 2003) - Corrected typo.
Revision 1.
3 (January, 2004) - Corrected typo in functional block diagram of 1GB DIMM Revision 1.
4 (February, 2004) - Corrected functional block diagram of 1GB DIMM
DDR SDRAM
Revision 1.
4 February, 2004
256MB, 512MB, 1GB Registered DIMM
184Pin Registered DIMM based on 256Mb E-die (x4, x8)
Ordering Information
Part Number M383L3223ETS-CAA/A2/B0/A0 M383L6423ETS-CAA/A2/B0/A0 M383L6420ETS-CAA/A2/B0/A0 M383L2828ET1-CAA/A2/B0/A0 M312L3223ETS-CAA/A2/B0/A0 M312L6423ETS-CAA/A2/B0/A0 M312L6420ETS-CAA/A2/B0/A0 M312L2828ET0-CAA/A2/B0/A0 Density 256MB 512MB 512MB 1GB 256MB 512MB 512MB 1GB Organization 32M x 72 64M x 72 64M x 72 128M x 72 32M x 72 64M x 72 64M x 72 128M x 72
DDR SDRAM
Component Composition 32Mx8( K4H560838E) * 9EA 32Mx8( K4H560838E) * 18EA 64Mx4( K4H560438E) * 18EA st.
128Mx4( K4H510638E) * 18EA 32Mx8( K4H560838E) * 9EA 32Mx8( K4H560838E) * 18EA 64Mx4( K4H560438E) * 18EA st.
128Mx4( K4H510638E) * 18EA
Height 1,700mil 1,700mil 1,700mil 1,700mil 1,200mil 1,200mil 1,200mil 1,200mil
Operating Frequencies
AA(DDR266@CL=2) Speed @CL2 Speed @CL2.
5 CL-tRCD-tRP 133MHz 133MHz 2-2-2 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.
5) 100MHz 133MHz 2.
5-3-3 A0(DDR200@CL=2) 100MHz 2-2-2
Feature
• Power supply : Vdd: 2.
5V ± 0.
2V, Vddq: 2.
5V ± 0.
2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.
5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interlea...
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