N-channel TrenchMOS ultra low level FET
Description
PH2925U
N-channel TrenchMOS™ ultra low level FET
M3D748
Rev.
02 — 08 April 2004
Product data
1.
Product profile
1.
1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology.
1.
2 Features
s Low thermal resistance s Low threshold voltage s SO8 equivalent area footprint s Low on-state resistance.
1.
3 Applications
s DC-to-DC converters s Portable appliances s Switched-mode power supplies s Notebook computers.
1.
4 Quick reference data
s VDS ≤ 25 V s Ptot ≤ 62.
5 W s ID ≤ 100 A s RDSon ≤ 2.
9 mΩ
2.
Pinning information
Table 1: Pin 1,2,3 4 mb Pinning - SOT669 (LFPAK), simplified outline and symbol Description source (s)
mb d
Simplified outline
Symbol
gate (g) mounting base; connected to drain (d)
g s
MBB076
1
2
3
4
MBL286
Top view
SOT669 (LFPAK)
Philips Semiconductors
PH2925U
N-channel TrenchMOS™ ultra low level FET
3.
Ordering information
Table 2: Ordering information Package Name PH2925U LFPAK Description Plastic single-ended surface mounted package; 4 leads Version SOT669 Type number
4.
Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter VDS VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 70.
7 A; tp = 0.
22 ms; VDD ≤ 25 V; VGS = 10 V; starting Tj = 25 °C Tmb = 25 °C; VGS = 4.
5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 4.
5 V; Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 150 °C Min −55 −55 Max 25 ±10 100 71 300 62.
5 +150 +150 52 150 250 Unit V V A A A W °C °C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
9397 750 13064
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