2M x 32-Bit Dynamic RAM Module
Description
2M × 32-Bit Dynamic RAM Module (Hyper Page Mode - EDO Version)
HYM 322005S/GS-50/-60
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SIMM modules with 2 097 152 words by 32-bit organization for PC main memory application Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) Hyper page mode - EDO capability with 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) Single + 5 V (± 10 %) supply Low power dissipation max.
2200 mW active (-50 version) max.
1980 mW active (-60 version) CMOS – 22 mW standby TTL – 44 mW standby CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh 4 decoupling capacitors mounted on substrate All inputs, outputs and clock fully TTL compatible 72 pin Single in-Line Memory Module Utilizes four 1M × 16 -DRAMs in SOJ-42 packages 1024 refresh cycles / 16 ms Optimized for use in byte-write non-parity applications Tin-Lead contact pad HYM 322005S Gold-Lead contact pad HYM 322005GS single sided module with 20.
32 mm (800 mil) height
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Semiconductor Group
1
9.
96
HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module
The HYM 322005S/GS-50/-60 is a 8 MByte EDO - DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5118160BSJ 1M × 16 EDO - DRAMs in 400 mil wide SOJ-packages mounted together with four 0.
2 µF ceramic decoupling capacitors on a PC board.
Each HYB 5118165BSJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly.
After assembly onto the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use presence detect pins.
The common I/O feature on the HYM 322005S/GS-50/-60 dictates the use of early write cycles.
Ordering Information Type HYM 322005S-50 HYM 322005S-60 HYM 322005GS-50 HYM 322005GS-60 Ordering Code Q67100-Q2066 Q67100-Q2067 Q67100-Q2068 Q67100-Q2069 Package L-SIM-72-10 L-SIM-7...
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