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74LS196

Motorola

4-STAGE PRESETTABLE RIPPLE COUNTERS - Motorola


74LS196
74LS196

PDF File 74LS196 PDF File



Description
4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output.
The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter.
Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW.
A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops.
This preset feature makes the circuits usable as programmable counters.
The circuits can also be used as 4-bit latches, loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH.
SN54/74LS196 SN54/74LS197 4-STAGE PRESETTABLE RIPPLE COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 14 1 • • • • • • • Low Power Consumption — Typically 80 mW High Counting Rates — Typically 70 MHz Choice of Counting Modes — BCD, Bi-Quinary, Binary Asynchronous Presettable Asynchronous Master Reset Easy Multistage Cascading Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 MR 13 Q3 12 P3 11 P1 10 Q1 9 CP0 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 PL 2 Q2 3 P2 4 P0 5 Q0 6 CP1 7 GND PIN NAMES LOADING (Note a) HIGH LOW 1.
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8 6 LOGIC SYMBOL 1 PL 4 10 3 11 P0 P1 P2 P3 CP0 CP1 (LS196) CP1 (LS197) MR PL P0–P3 Q0–Q3 Clock (Active LOW Going Edge) Input to Divide-by-Two S...



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