3V DUAL DOWNCONVERTER AND PLL FREQUENCY SYNTHESIZER
Description
PRELIMINARY DATA SHEET
3V DUAL DOWNCONVERTER AND PLL FREQUENCY SYNTHESIZER
UPB1004GS
FEATURES
• INTEGRATED RF BLOCK: RF & IF Downconverter + PLL frequency synthesizer
• DOUBLE-CONVERSION: f1stIF = 61.
380 MHz f2ndIF = 4.
092 MHz
• ADJUSTABLE GAIN: 20 dB range MIN • FIXED DIVISION PRESCALER • LOW POWER CONSUMPTION: 37.
5 mA @ 3 V • SMALL 30 PIN SSOP PACKAGE • TAPE AND REEL PACKAGING AVAILABLE
DESCRIPTION
The UPB1004GS is a Silicon Monolithic Integrated Circuit designed for low cost GPS receivers.
The IC combines a double-conversion RF/IF downconverter block and a PLL frequency synthesizer on one chip.
The device operates on a 3 V supply voltage and is housed in a small 30 pin SSOP package, resulting in low power consumption and reduced board space.
The device is manufactured using the NESAT™ III 20 GHz fT silicon bipolar process.
NEC's stringent quality assurance and test procedures ensure the highest reliability and performance.
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3 V, unless otherwise specified)
PART NUMBER PACKAGE OUTLINE
UPB1004GS S30
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
ICC Total Circuit Current, No Signals
mA 31.
1
RF Downconverter Block (fRFin = 1575.
42 MHz, f1stLOin = 1636.
80 MHz, PLOin = -10 dBm, ZL = ZS = 50 Ω)
ICC1 Circuit Current 1, No Signals
mA 7.
2
CGRF
RF Conversion Gain, PRFin = -40 dBm
dB 9.
5
NFRF
RF SSB Noise Figure, PRFin = -40 dBm
dB
PO(sat)RF Maximum IF Output, PRFin = -10 dBm
dBm
-8
LOIF
LO Leakage to IF Pin, fLOin = 1636.
80 MHz
dBm
LORF
LO Leakage to RF Pin, fLOin = 1636.
80 MHz
dBm
IIP3RF Input 3rd Order Intercept Point, fRFin1 = 1600 MHz,
fRFin2 = 1605 MHz, fLOin = 1570 MHz
dBm
IF Downconverter Block (f1stIFin = 61.
38 MHz, f2ndLOin = 65.
472 MHz, ZS = 50 Ω, ZO = 2 kΩ)
ICC2 Circuit Current 2, No Signals
mA 2.
7
CGIF
IF Conversion Gain at Max.
Gain, P1stIFin = -50 dBm
dB
37
NFIF
IF SSB Noise Figure at Max.
Gain, P1stIFin = -50 dBm
dB
12
PO(sat)IF
Maximum 2nd IF Output Level at Max.
Ga...
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