6-Bit D Register
Description
SK10/100E151
6-Bit D Register
HIGH-PER.
ORMANCE PRODUCTS Description
The SK10/100E151 offers 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new high-performance ECL systems.
This device is fully compatible with MC10E151 and MC100E151.
The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops.
Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both).
When both CLK1 and CLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK or CLK2 (or both) go HIGH.
The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW.
.
eatures
• • • • • • • • • • 1100 MHz Toggle Frequency Extended 100E VEE Range of –4.
2V to –5.
46V Differential Outputs Asynchronous Master Reset Dual Clocks Internal 75KΩ Input Pull-Down Resistors ESD Protection of >4000V Fully Compatible with MC10E/100E151 Specified Over Industrial Temperature Range: –40oC to +85oC Available in 28-Pin PLCC Package
PIN Description .
unctional Block Diagram
Pin D0D5 CLK1, CLK2
D0 D R Q0 Q0*
.
unction Data Inputs Clock Inputs Master Reset True Outputs Inver ting Outputs VCC to Output
MR Q0Q5
D1
D R
Q1 Q1*
Q0*Q5* VCC0
D2
D R
Q2 Q2*
VCC0
CLK2
CLK1
D3
D R
Q3
MR
Q5* 20
NC
Q3*
25 24 23 22 21 19
D4
D R
Q4 Q4*
D5 D4 D3
26 27 28 1 2 3 4
10 11 5 6 7 8 9
Q5
18 17 16
Q4* Q4 VCC Q3* Q3 Q2* Q2
D5
D R
Q5 Q5*
VEE D2 D1 D0
PLCC TOP VIEW
15 14 13 12
CLK1 CLK2 MR
Q0
NC
Q0*
Q1
VCC0
Q1*
VCC0
Revision 1/.
ebruary 13, 2001
1
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SK10/100E151
HIGH-PER.
ORMANCE PRODUCTS PIN Description (continued)
Truth Tables
Inputs Dn X CLK1 X CLK2 X MR H Output Qn(t+1) L
Inputs Dn L H L CLK1 u u L L H u L CLK2 L L u u u H L MR L L L L L L L
Output Qn(t+1) L H L H Qn(t) Qn(t) Qn(t)
Asynchronous Operation NOTES: 1.
2.
3.
4.
5.
6.
H = HIGH Voltage Level L = LOW Voltage Level...
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