4-Bit D Flip-Flop
Description
SK10/100E131
HIGH-PER.
ORMANCE PRODUCTS Description
The SK10E/100E131 is a Quad master-slave D-type flipflop with differential outputs.
Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE*) inputs for clocking.
Common clocking is achieved by holding the CE inputs LOW and using CC to clock all four flip-flops.
In this case, the CE* inputs perform the function of controlling the common clock to each flip-flop.
4-Bit D .
lip-.
lop
Features
• • • • • • • • 1100 MHz Minimum Toggle Frequency Differential Outputs Individual and Common Clocks Individual Resets (asynchronous) Paired Sets (asynchronous) Extended 100E VEE Range of –4.
2V to –5.
5V 75KΩ Internal Input Pulldown Resistors Fully Compatible with MC10E131 and MC100E131 Specified Over Industrial Temperature Range: –40oC to 85oC ESD Protection of >4000V Available in 28-pin PLCC Package
Individual asynchronous resets are provided (R).
• Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip • symmetry.
• Data enters the master when both CC and CE* are LOW, and transfers to the slave when either CC or CE (or both) go HIGH.
PIN Description
Pin Names
Functional Block Diagram
Pin D0 - D3 CE0* - CE3* R0 - R3 CC S03, S12 Q0 - Q3 Q0* - Q3*
.
unction Data Inputs Clock Enables (individual) Resets Common Clock Sets (paired) True Outputs Inver ting Outputs
D3 CE3*
D
S
Q Q
Q3 Q3*
R R3
D2 CE2*
D
S
Q Q
Q2 Q2*
R R2 S03 S12 CC R1 R CE1* D1 D S
Pinout
VCC0 CE2* Q3*
20
25 CE3* D3 S12 VEE 26 27 28
24
23
22
21
Q3
19 18 17 16 Q2* Q2 VCC Q1* Q1 Q0* Q0 15 14 13 12 11
R3
D2
Q Q
Q1* Q1
28 Lead PLCC
1 (Top View) 2 3 4 5 6 7 8 9 10 CC
R0 R CE0* D0 D S Q Q Q0* Q0
S03 D0
R2
VCC0
CE0*
CE1*
R0
R1
NC
D1
Revision 1/.
ebruary 13, 2001
1
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SK10/100E131
HIGH-PER.
ORMANCE PRODUCTS Package Information
Y BRK –N–
A Z
D
0.
007 (0.
180) M T L – M 0.
007 (0.
180)
M
S S
NS NS
R
T L–M
PIN Descriptions
–L–...
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