Octal Bus Transceiver and Register
Description
DM74AS651 • DM74AS652 Octal Bus Transceiver and Register
October 1986 Revised March 2000
DM74AS651 • DM74AS652 Octal Bus Transceiver and Register
General Description
These devices incorporate an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus.
The DM74AS651 offers 64-Industrial grade product guaranteeing performance from −40°C to +85°C.
These bus transceivers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads.
The high-impedance state and increased high-logic-level drive provide these devices with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components.
They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The registers in the DM74AS651 and DM74AS652 are edge-triggered D-type flip-flops.
On the positive transition of the clock (CAB or CBA), the input data is stored.
The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred.
A LOW input level selects real-time data and a HIGH level selects stored data.
The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.
The Enable (GAB and GBA) control pins provide four modes of operation; real-time data transfer from bus A-toB, real-time data transfer from bus B-to-A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B.
Features
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer-type outputs drive bus lines directly s Guaranteed performan...
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