DatasheetsPDF.com

ADC10040

National Semiconductor

10-Bit/ 40 MSPS/ 3V/ 55.5 mW A/D Converter


ADC10040
ADC10040

PDF File ADC10040 PDF File


Description
ADC10040 10-Bit 40 MSPS 3V, 55 mW A/D Converter November 2004 ADC10040 10-Bit, 40 MSPS, 3V, 55.
5 mW A/D Converter General Description The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS).
This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance.
A unique sample-and-hold stage yields a fullpower bandwidth of 400 MHz.
Operating on a single 3.
0V power supply, this device consumes just 55.
5 mW at 40 MSPS, including the reference current.
The Standby feature reduces power consumption to just 13.
5 mW.
The differential inputs provide a full scale selectable input swing of 2.
0 VP-P, 1.
5 VP-P, 1.
0 VP-P, with the possibility of a single-ended input.
Full use of the differential input is recommended for optimum performance.
An internal +1.
2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy.
The output data format is 10-bit offset binary, or two’s complement.
This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40˚C to +85˚C.
Features n Single +3.
0V operation n Selectable 2.
0 VP-P, 1.
5 VP-P, or 1.
0 VP-P full-scale input swing n 400 MHz −3 dB input bandwidth n Low power consumption n Standby mode n On-chip reference and sample-and-hold amplifier n Offset binary or two’s complement data format n Separate adjustable output driver supply to accommodate 2.
5V and 3.
3V logic families n 28-pin TSSOP package Key Specifications n n n n n n n n n Resolution Conversion Rate Full Power Bandwidth DNL SNR (fIN = 11 MHz) SFDR (fIN = 11 MHz) Data Latency Supply Voltage Power Consumption, 40 MHz ...



Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)