DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
Description
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS046A – MARCH 1987 – REVISED OCTOBER 1993
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
description
These devices contain two independent positiveedge-triggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54F74 is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74F74 is characterized for operation from 0°C to 70°C.
SN54F74 .
.
.
J PACKAGE SN74F74 .
.
.
D OR N PACKAGE
(TOP VIEW)
1CLR 1 1D 2
1CLK 3 1PRE 4
1Q 5 1Q 6 GND 7
14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q
SN54F74 .
.
.
FK PACKAGE (TOP VIEW)
1D 1CLR NC VCC 2CLR
1CLK NC
1PRE NC 1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2D NC 2CLK NC 2PRE
1Q GND
NC 2Q 2Q
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H† H†
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0 Q0
† The output levels are not guaranteed to meet the
minimum levels for VOH.
Furthermore, this configuration is nonstable; that is, it will not persist
when PRE or CLR returns to its inactive (high)
level.
NC – No internal connection
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all par...
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