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ADC083000

Texas Instruments

Low Power A/D Converter


ADC083000
ADC083000

PDF File ADC083000 PDF File


Description
ADC083000 www.
ti.
com SNAS358N – JUNE 2006 – REVISED JULY 2009 ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter Check for Samples: ADC083000 FEATURES 1 •2 Single +1.
9V ±0.
1V Operation • Choice of SDR or DDR Output Clocking • Serial Interface for Extended Control • Adjustment of Input Full-Scale Range and Offset • Duty Cycle Corrected Sample Clock • Test Pattern APPLICATIONS • Direct RF Down Conversion • Digital Oscilloscopes • Satellite Set-Top Boxes • Communications Systems • Test Instrumentation KEY SPECIFICATIONS • Resolution 8 Bits • Max Conversion Rate 3 GSPS (min) • Error Rate 10-18 (typ) • ENOB @ 748 MHz Input 7.
0 Bits (typ) • SNR @ 748 MHz 44.
5 dB (typ) • Full Power Bandwidth 3 GHz (typ) • Power Consumption – Operating 1.
9 W (typ) – Power Down Mode 25 mW (typ) DESCRIPTION The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.
4 GSPS.
Consuming a typical 1.
9 Watts at 3 GSPS from a single 1.
9 Volt supply, this device is specified to have no missing codes over the full operating temperature range.
The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the selfcalibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.
0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10-18 Word Error Rate.
The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.
5 GHz input clock.
Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.
3-1996, with the exception of an adjustable common mode voltage between 0.
8V and 1.
15V.
The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate.
The converter...



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