16-Bit 195kSPS CMOS Sigma-Delta ADC
Description
a
FEATURES 16-Bit Sigma-Delta ADC 64 ؋ Oversampling Ratio Up to 220 kSPS Output Word Rate Low-Pass, Linear Phase Digital Filter Inherently Monotonic On-Chip 2.
5 V Voltage Reference Single Supply +5 V High Speed Parallel or Serial Interface
16-Bit, 195 kSPS CMOS, Sigma-Delta ADC AD7722
FUNCTIONAL BLOCK DIAGRAM
DGND DVDD AGND AVDD REF1
AD7722
2.
5V REFERENCE
REF2
VIN(+) VIN(–)
16-BIT A/D CONVERTER Σ∆ MODULATOR FIR FILTER
P/S CAL RESET SYNC CS DVAL/RD CFMT/DRDY DB0 DB1 DB2 CONTROL LOGIC
CLOCK CIRCUITRY
XTAL CLKIN UNI DB15 DB14 DB13 DB12 DB11 DB10 DB9/FSO
GENERAL DESCRIPTION
The AD7722 is a complete low power, 16-bit, sigma-delta ADC.
The part operates from a +5 V supply and accepts a differential input voltage range of 0 V to +2.
5 V or ± 1.
25 V centered around a common-mode bias.
The AD7722 provides 16-bit performance for input bandwidths up to 90.
625 kHz.
The part provides data at an output word rate of 195.
3 kHz.
The analog input is continuously sampled by an analog modulator eliminating the need for external sample-and-hold circuitry.
The modulator output is processed by two Finite Impulse Response (FIR) digital filters in series.
The on-chip filtering reduces the external antialias requirements to first order, in most cases.
The group delay for the filter is 215.
5 µs, while the settling time for a step input is 431 µs.
The sample rate, filter corner frequency, and output word rate are set by an external clock that is nominally 12.
5 MHz.
Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy.
Endpoint accuracy is ensured by onchip calibration.
This calibration procedure minimizes the zeroscale and full-scale errors.
DB3/ TSI
DB4/ DB5/ DB6/ DB7/ DB8/ DOE SFMT FSI SCO SDO
Conversion data is provided at the output register through a flexible serial port or a parallel port.
This offers 3-wire, high speed interfacing to digital signal processors.
The serial interface operates in an internal clocking (master) mode, whereby an ...
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