1.8V to 3.3V LVCMOS High Performance Clock Buffer
Description
1.
8V to 3.
3V LVCMOS High-Performance Clock Buffer Family
5PB11xx
DATASHEET
Description
The 5PB11xx is a high-performance LVCMOS clock buffer family.
It has best-in-class additive phase jitter of 50fsec RMS.
There are five different fan-out variations available: 1:2 to 1:10.
The 5PB11xx also supports a synchronous glitch-free output enable (OE) function to eliminate any potential intermediate incorrect output clock cycles when enabling or disabling outputs.
It’s available in various packages and can operate from a 1.
8V to 3.
3V supply.
Features
• High-performance 1:2, 1:4, 1:6, 1:8, 1:10 LVCMOS clock
buffer
• Very low pin-to-pin skew < 50ps • Very low additive jitter < 50fs • Supply voltage: 1.
8V to 3.
3V • 3.
3V tolerant input clock • fMAX = 200MHz • Integrated serial termination for 50 channel • Packaged in 8-, 14-, 16-, 20-pin TSSOP and as small as
2 × 2 mm DFN and QFN packages
• Industrial (-40°C to +85°C) and extended (-40°C to
+105°C) temperature ranges
Block Diagram
CLKIN
LVCMOS
LVCMOS
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
Yn
1G
5PB11xx FEBRUARY 20, 2018
1 ©2018 Integrated Device Technology, Inc.
5PB11xx DATASHEET
Pin Assignments for TSSOP Packages
CLKIN 1G Y0
GND
1 2 3 4
5PB1102PGG
8 Y1 7 NC 6 VDD 5 NC
CLKIN 1G Y0
GND
1 2 3 4
5PB1104PGG
8 Y1 7 Y3 6 VDD 5 Y2
CLKIN 1G Y0
GND VDD
Y4 GND
1 2 3 4 5 6 7
5PB1106PGG
14 Y1 13 Y3 12 VDD 11 Y2 10 GND
9 Y5 8 VDD
CLKIN 1G Y0
GND VDD
Y4 GND
Y6
1 2 3 4 5 6 7 8
5PB1108PGG
16 Y1 15 Y3 14 VDD 13 Y2 12 GND
11 Y5 10 VDD 9 Y7
CLKIN 1 1G 2 Y0 3
GND 4 VDD 5
Y4 6 GND 7
Y6 8 VDD 9
Y9 10
5PB1110PGG
20 Y1 19 Y3 18 VDD 17 Y2 16 GND
15 Y5 14 VDD 13 Y7 12 Y8 11 GND
Pin Descriptions for TSSOP Packages
Device Number
5PB1102PGG 5PB1104PGG 5PB1106PGG 5PB1108PGG 5PB1110PGG
LVCMOS Clock Input
CLKIN
1 1 1 1 1
Clock Output Enable
LVCMOS Clock Output
1G Y0, Y1, .
.
.
Y9
2 3, 8
2 3, 8, 5, 7
2 3, 14, 11, 13, 6, 9
2 3, 16, 13, 15, 6, 11, 8, 9
2 3, 20, 17, 19, 6, 15, 8, 13, 12, 10
Supply Voltage
VDD ...
Similar Datasheet
