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CD74HC02

High-Speed CMOS Logic Quad Two-Input NOR Gate - Texas Instruments

CD74HC02 PDF File

Description

Data sheet acquired from Harris Semiconductor SCHS125C March 1998 - Revised September 2003 CD54HC02, CD74HC02, CD54HCT02, CD74HCT02 High-Speed CMOS Logic Quad Two-Input NOR Gate [ /Title (CD74H C02, CD74H CT02) /Subject (High Speed CMOS Logic Quad Two- Features Description • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 7ns at VCC = 5V, • Fanout (Over Temperature Range) - Standard Outputs .
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10 LSTTL Loads - Bus Driver Outputs .
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15 LSTTL Loads • Wide Operating Temperature Range .
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-55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.
5V to 5.
5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.
8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC02 and ’HCT02 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits.
All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the standard LS logic family.
Ordering Information PART NUMBER CD54HC02F3A CD54HCT02F3A CD74HC02E CD74HC02M CD74HC02MT CD74HC02M96 CD74HCT02E CD74HCT02M CD74HCT02MT TEMP.
RANGE (oC) PACKAGE -55 to 125 14 Ld CERDIP -55 to 125 14 Ld CERDIP -55 to 125 14 Ld PDIP -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC -55 to 125 14 Ld PDIP -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC CD74HCT02M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number.
The sufﬁx 96 denotes tape and reel.
The sufﬁx T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments ...

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